Learn Digital Designing Using Verilog

Verilog is a Hardware Description Language used to model and synthesize digital systems. Applied to electronic design, Verilog is used for verification via simulation, for timing analysis, logic synthesis and test analysis. The course offered by us combines insightful lectures as well as practical exercises to reinforce basic concepts. Students can also learn advanced coding techniques that will increase their overall Verilog proficiency.


Course Duration: 1 Month

Course objectives:

This course will provide an overview of the Verilog with the following objectives:

  • Explain design, test and implementation of digital hardware
  • Explain the hierarchy and modelling of structures
  • Introduces syntax, lexical conventions, data types and memory
  • Behavioural and register transfer level modelling
  • Explain how to write RTL Verilog code for synthesis
  • In-depth understanding of gate level modelling
  • Explains the concept of delays, test benches, timing checks, etc.

  • Delegates will be able to:

  • Design, simulate and synthesize and computer hardware with Verilog
  • Design combinational and sequential logic that works
  • Synthesize logic and state machines using automatic logic synthesis program
  • Implement state machines using Field-Programmable Gate Arrays
  • Run a timing simulation using Verilog libraries
  • Evaluate testability using fault simulation methods
  • Use enhanced Verilog file I/O capability
  • How to build models using loops, assignment, process statements, if and case statements.

  • Course Content

  • Language introduction
  • Levels of abstraction
  • Module, Ports types and declarations
  • Registers and nets, Arrays
  • Identifiers, Parameters
  • Relational, Arithmetic, Logical, Bit-wise shift Operators
  • Writing expressions
  • Behavioral Modeling
  • Structural Coding
  • Continuous Assignments
  • Procedural Statements
  • Always, Initial Blocks, begin ebd, fork join
  • Blocking and Non-blocking statements
  • Operation Control Statements
  • If, case
  • Loops: while, for-loop, forever, repeat
  • Combination and sequential circuit designs
  • Memory modeling,, state machines
  • CMOS gate modeling
  • Writing Tasks
  • Writing Functions
  • Compiler directives
  • Conditional Compilation
  • System Tasks
  • Gate level primitives
  • User defined primitives
  • Delays, Specify block
  • Testbenchs, modeling, timing checks
  • Assertion based verification
  • Code for synthesis
  • Advanced topics
  • Writing reusable code
  • Students with little or no Verilog knowledge will finish our course empowered with the ability to model efficient digital systems and perform high-level simulations in the industries.

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